1. Field of the Invention
The present invention relates to a static random access memory (SRAM) and a method of manufacturing the same. More particularly, the present invention relates to an asymmetrical SRAM device that can prevent leakage current and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor devices can be classified as dynamic random access memory (DRAM), nonvolatile memory, or SRAM. SRAM offers advantages of high speed operation, low power consumption, and a simple operation method. Additionally, SRAM has an advantage of easy design, since information stored therein does not require refreshing periodically, as does DRAM.
SRAM includes a pair of inverters operating in opposite phase from each other. A conventional SRAM has a symmetrical configuration in which each of a pair of inverters performs the same function.
FIG. 1 is a circuit diagram of a unit cell of a conventional SRAM device.
As depicted in FIG. 1, a full complementary metal oxide semiconductor (CMOS) SRAM having a pair of inverters includes first and second inverters INV1 and INV2 that constitute a latch and first and second pass transistors N3 and N4 connected to an output of the first and second inverters INV1 and INV2, respectively.
The first inverter INV1 includes a first positive channel metal oxide semiconductor (PMOS) transistor P1 and a first negative channel metal oxide semiconductor (NMOS) transistor N1. The second inverter INV2 includes a second PMOS transistor P2 and a second NMOS transistor N2. The sources of each of the PMOS transistors P1 and P2 are connected to a power source voltage VDD, and the drains are connected to the first and second NMOS transistors N1 and N2, respectively. The sources of each of the first and second NMOS transistors N1 and N2 are connected to a ground VSS. An input of the first inverter INV1 is connected to an output S2 of the second inverter INV2, and an input of the second inverter INV2 is connected to an output S1 of the first inverter INV1.
The first pass transistor N3 has a gate connected to a word line WL, a drain connected to a bit line BL, and a source connected to the output S1 of the first inverter INV1. The second pass transistor N4 has a gate connected to the word line WL, a drain connected to a bit line bar DBL, and a source connected to the output S2 of the second inverter INV2. Here, the bit line bar DBL is applied to an inverted bit line signal.
The full CMOS SRAM device is operated in the following manner. When a potential of the word line WL is “1,” i.e., high, the first and second pass transistors N3 and N4 are turned “on,” and signals of the bit lines BL and DBL are transmitted to the first and second inverters INV1 and INV2, respectively. Writing or reading of data can then be performed.
However, more “0” data than “1” data is stored in the SRAM cells that are output by the first inverter INV1. Therefore, a leakage current occurs in a particular transistor that constitutes the SRAM cell because the data stored in the SRAM device is biased to “0”.
More specifically, when reading data, the bit line BL and the bit line bar DBL are precharged to “1,” and “0” is applied to the word line WL. When the output of the first inverter INV1 is “0” and the output of the second inverter INV2 is “1”, leakage current is generated at the transistors, in which a potential difference is generated between the source and the drain, i.e., the first PMOS transistor P1, the second NMOS transistor N2, and the first pass transistor N3.
A conventional method of solving this problem sought to improve the threshold voltage of the transistors that cause the leakage current. FIG. 2 is a circuit diagram of a unit cell of a conventional asymmetrical SRAM device in this conventional method. As illustrated in FIG. 2, when the output S1 of the first inverter INV1 is “0”, the transistors that generate leakage current, such as the first PMOS transistor (P1 of FIG. 1), the second NMOS transistor (N2 of FIG. 1), and the first pass transistor (N3 of FIG. 1), are replaced by high voltage transistors HP1, HN2, and HN3, respectively. Accordingly, the leakage current of the first PMOS transistor, the second NMOS transistor, and the first pass transistor may be reduced.
FIG. 3 is a circuit diagram of a sense amplifier applied to the conventional asymmetrical SRAM device in FIG. 2.
The asymmetrical SRAM device has a stable static noise margin (SNM) when the stored data is “0.” When the stored data is “1”, however, there is a high possibility of generating an error. A sense amplifier, as illustrated in FIG. 3, has been proposed in connection with this conventional method to compensate for the error. The proposed sense amplifier has a structure in which a complementary transistor block T is connected to a conventional sense amplifier. Data “1” is continuously stored in D of the complementary transistor block T and data “0” is continuously stored in DB. Errors in the SRAM device when data is “1” can be prevented by employing the modified sense amplifier.
FIG. 4 illustrates a plan view, i.e., a layout, of a unit cell of the conventional asymmetrical SRAM device shown in FIG. 2. Referring to FIG. 4, an isolation film 15 is formed in a semiconductor substrate 10. The isolation film 15 defines a first active region 30, on which NMOS transistors N1 through N4 will be formed, and a second active region 50, on which PMOS transistors P1 and P2 will be formed, on the silicon semiconductor substrate 10. The first active region 30 is a region for forming a P well in a “U” shape. Here, portions of both sidewalls of the “U” shape will be called vertical portions and a portion that connects both vertical portions will be called a horizontal portion. The second active region 50 is a region for forming an N well in a “-” shape, i.e., a bar shape.
A word line WL extends at right angles to the vertical portions of the first active region 30, and first and second gate lines 60 and 65 are formed to contact a horizontal portion of the first active region 30 and a predetermined portion of the second active region 50. The word line WL becomes the gate electrode of the first and second pass transistors N3 and N4. The first gate line 60 becomes the gate electrode of the first PMOS transistor P1 and the first NMOS transistor N1. The second gate line 65 becomes the gate electrode of the second PMOS transistor P2 and the second NMOS transistor N2.
The first and second pass transistors N3 and N4 and the first and second NMOS transistors N1 and N2 are defined by implanting an N-type dopant in the first active region 30 on both sides of the word line WL and of the gate lines 60 and 65. The first and second PMOS transistors P1 and P2 are formed by implanting a P-type dopant in the second active region 50 on both sides of the first and second gate lines 60 and 65.
In FIG. 4, BLC indicates a region for forming a contact to connect the drain of the first pass transistor N3 and the bit line BL, and DBLC indicates a region for forming a contact to connect the drain of the second pass transistor N4 and the bit line bar DBL. S1 and S1′, and S2 and S2′ indicate the outputs of the inverters INV1 and INV2, respectively. In the drawing, S1 and S1′, and S2 and S2′ are illustrated separately, but they will be connected when forming wiring in a subsequent process. VDD is a region to be connected to a power source line, and VSS is a region to be connected to a ground line. GC is a region to be connected to the gate electrode and a gate power source line (not shown).
To manufacture an asymmetrical SRAM device, the threshold voltages of the first PMOS transistor P1, the second NMOS transistor N2, and the first pass transistor N3 must be increased. To increase the threshold voltages, threshold voltage control ions for high voltage transistors must be implanted into regions of the first PMOS transistor P1, the second NMOS transistor N2, and the first pass transistor N3. When implanting the threshold voltage control ions, an additional photomask is required, exposing only the regions of the first PMOS transistor P1, the second NMOS transistor N2, and the first pass transistor N3.
However, as the integration density of semiconductor devices increases, gaps between the each of the transistor regions of the SRAM device decrease, and a gap of a mask pattern that can be formed by photolithography reaches a limit thereof.
Therefore, it is difficult to selectively expose the first PMOS transistor P1, the second NMOS transistor N2, and the first pass transistor N3 in the narrow unit SRAM cell region.
As illustrated in FIG. 4, the first PMOS transistor P1 and the second PMOS transistor P2 are very close to each other, the second NMOS transistor N2 is very close to the first NMOS transistor N1 and the second pass transistor N2, and the third pass transistor N3 is also close to the first NMOS transistor N1.
Therefore, problems may occur when changing the threshold voltage of the MOS transistors that constitute the SRAM cell, since other adjacent transistors may be exposed when opening the regions of the first PMOS transistor P1, the second NMOS transistor N2, and the first pass transistor N3.